This is Part 1 of a Two Part Series

• Decoupling Part 1:The Basics
• Decoupling Part 2:Low Inductance MLCCs

One of the largest uses of ceramic capacitors in the electronics industry is for decoupling.  Decoupling is commonly referred to as a methodology used to provide a localized source of electrical energy to a circuit in order to prevent unwanted changes to the supply voltage.  Decoupling is commonly used in power delivery circuits in an application that involves a relatively high switching load.  Typical examples include power supplies and microprocessors. 

What happens?

For example, when the switching demand becomes too high at a microprocessor, the supply voltage may “droop” or be reduced to a level that is unacceptably low for the “on” state of one or more switches within the microprocessor.  When this occurs, switch state errors can happen and the microprocessor may either crash or do something different than you asked it too.  In order to prevent this from happening, designers place decoupling capacitors local to the microprocessor from the power line to ground.  In this configuration, the decoupling capacitors charge to the supply voltage value during normal operation, while blocking DC power transfer to ground.  When the switching load at the microprocessor becomes high, the charged, local decoupling capacitors become local energy sources as the supply voltage begins to drop due to the high demand at the microprocessor.  These “little batteries” quickly supply charge to the supply power in order to ensure that the supply voltage is maintained during conditions of high load from the microprocessor.  In that manner, they “decouple” the microprocessor from the power supply.

So now that we know what decoupling is, what are some “rules of thumb” with regard to decoupling?  From the most basic standpoint, we want to ensure that enough charge is always available to the load and that it is available quickly enough to prevent unacceptable voltage droop (or unacceptable change in waveform) and we want to do this all in an economic manner.  But first we will cover some decoupling history in order to provide perspective.

History of Decoupling

Approaches to decoupling have changed over time.  Originally, multiple tiers of decoupling were used and the each tier decoupled into another tier closer to the load.  Typically very high value aluminum electrolytic capacitors would be used at the power supply which would serve to provide third tier decoupling to tantalum capacitors placed midway between the power supply and the microprocessor, which would provide second tier decoupling to ceramic capacitors placed near the microprocessor load, which provided first tier decoupling to the load or microprocessor.  While this methodology works well, it is relatively expensive and design engineers have spent considerable resources finding simpler schemes for decoupling.

As power supplies have evolved over time to higher switching frequencies, tier 3 and tier 2 have been reduced or combined or eliminated and an emphasis has been placed on power distribution quality of the power supply to tier 1 and the load over a broad range of frequencies.  Additionally, the evolution of microprocessors to include more on chip decoupling capacitance (tier 0) has somewhat reduced, the demands for tier 1 decoupling in general.  Additionally, microprocessor switching frequencies have largely stabilized over time due to power savings requirements as well as the advent of multicore microprocessors.  All of these factors have resulted in an evolution in decoupling that has enabled more economical, smaller, and generally better power distribution to a microprocessor (or switching load).

This leaves optimization of tier 1 decoupling.  The goal of Tier 1 decoupling is to feed enough charge to tier 0 decoupling capacitance, resident within the microprocessor quickly enough to prevent significant voltage droop or other signal degradation.  Multilayer ceramic capacitors (MLCCs), with their small size and low ESR (i.e., ability to discharge very quickly) are ideal for this application and as such are the capacitor of choice for this application. 

Some Guidelines

The amount of capacitance that you need will depend upon your situation (mostly switching speed and switching energy).  The effect of the combination of switching speed and switching energy upon voltage droop is characterized by the equation:      

• V_Droop is voltage droop                  
• I is current (Amperes)
• ω is angular frequency (f) and is equal to 2πf
• C is capacitance (Farads)
• ESL is equivalent series inductance (Henries)
• ESR is equivalent series resistance (Ohms)

Typically multiple MLCCs are placed locally in parallel in a decoupling design.  The values depend upon the situation with more capacitance being needed at lower frequencies and lower ESL being needed at higher frequencies.  In practice, several each of several different capacitance values are placed locally;  tier 3 capacitors near the power supply and the tier 1 capacitors near the switching load or microprocessor. 

As an example, the above equation may be used to estimate maximum voltage droop in the case of multiple 10µF, 1µF, and 0.1µF and 0.01µF may be placed near the microprocessor to ensure that voltage droop is less than a specified value over a range of frequencies of interest.  If 10 each of the above 10µF, 1µF, and 0.1µF MLCCs and 20 each of the 0.01µF MLCCs are used very close to a microprocessor that can pull 25A at 2V with no more than 5% voltage droop allowed, the above configuration could be used to keep voltage droop less than 5% over the range of 1 MHz to 100 MHz.  The tier 0 capacitance (on chip) would be used to keep voltage droop low at higher frequencies (up to ~ 3Ghz or more).

The Process

In practice, the designer will determine the impedance needed for his or her power distribution network design using the relation:

where: Z is impedance (Ohms)

The designer will also calculate the tier 3 capacitance needed to ensure that the voltage does not droop below the acceptable limit at lower frequencies using the relation:

where: Δt_lf is the maximum allowable rise time for low frequency (sec)

The designer will also calculate the inductance that his or her design must stay below on the tier 1 side of the design using the relation:

where: Δt_hf is the minimum allowable rise time at highest frequency (sec)

 Other Considerations

All capacitors are placed in parallel in the circuit from power to ground.  When selecting capacitors for the lower frequency end of the spectrum (i.e., tier 3 and tier 2) the designer selects a combination of capacitors with high capacitance and low ESR in order to minimize V_Droop.  When selecting capacitors for the high frequency end of the application, the designer selects a combination of capacitors having lower capacitance and minimal ESL such that the circuit stays below the maximum impedance allowed at the high end of the application frequency range. 

Since a broad array of capacitance values will be used, it is important to select a combination of C, ESL and ESR that ensures avoidance of sharp peaks in Z due to anti-resonances between the different capacitance values placed in parallel.  The designer will also take advantage of the multiple resonance frequencies that a broad of capacitance values affords in order to minimize Z over a broad spectrum.

Circuit Design Considerations

It is also important to remember that, for tier 1 decoupling, the rest of the decoupling circuit design is important as well, as inductance of the entire circuit must be minimized.  To achieve this, tier 1 MLCCs are generally placed as close as possible to or directly on the microprocessor package.  To further reduce inductance, tier 1 MLCC may be placed on the back of the microprocessor package, directly beneath the microprocessor die.  To further ensure that circuit inductance is minimized, the MLCC connection to the circuit board, as well as the power and ground interconnects, should be designed to minimize current loops (inductance) using special solder pad and via design and placement, as well as use of multiple vias per mount where prudent. 

To reduce tier 1 inductance even further, use of specially designed, low ESL MLCCs may be used.  That will be the subject covered in Part 2 of this series.  I hope that you found this valuable…TTFN!