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Decoupling Part 2: Low ESL MLCCs

Posted by Mike Randall on August 14, 2014

 

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This is Part 2 of a Two Part Series

In my last post we discussed some decoupling basics, including multilayer ceramic capacitors (MLCCs) for tier 1 (high speed) decoupling.  In this post we discuss MLCC options for low inductance (ESL).  I hope that you find it useful as it is a fascinating subject to me, but first, some history.

History of MLCCs for High Speed Decoupling

Prior to the 1980s almost all electronics used plated through hole technology (PTH).  All MLCCs used were of leaded configuration and ESL values were quite high (typically >2,000 picoHenry (pH)).  As microprocessor technology advanced to higher frequencies and greater complexity, the need for high speed decoupling was recognized.  In the 1970s IBM developed their thermal conduction module (TCM) which utilized the ceramic multichip module (MCM), both “blockbuster” technologies at the time.  The technology was highly advanced, including high speed microprocessor technology and multiple other advanced technologies.  One highly advanced technology utilized was the use of low inductance “LICA” capacitors as the tier 1 decoupling solution. 

Enter the LICA

In conjunction with AVX, IBM invented and developed one of the first designed-for-purpose low inductance MLCCs called the low inductance capacitor array (LICA).  This device exhibited world leading performance, having ESL values of 50 (pH) or less.  However, LICA was very expensive, and was technically complex, using controlled-collapse-chip-connection (C4) technology, as well as interdigitated terminals for inductance cancellation, as well as enhanced electrode design and geometry for low ESL.  Because of its technical complexity, only certain manufacturers could use it and it was not adopted universally.  Nevertheless, it was a very impressive product and if you have an IBM mainframe, chances are you have some LICAs. 

Enter RGC MLCCs

Even though LICA’s performance was quite impressive, its cost and complexity left an unmet need for a “poor mans’ low inductance capacitor.”  The market needed a relatively low cost MLCC that could be easily mounted using standard SMD equipment, materials and techniques.  Reverse geometry capacitors (RGCs) are MLCCs having reversed electrode aspect ratio geometry, and that were developed to provide a solution for this need.   Example RGCs are pictured above.  Using RGC MLCCs resulted in an ESL reduction of about 60% or more compared to analogous standard configuration MLCCs.  Relatively low in cost and requiring only minor circuit design modification, RGC MLCCs represented an excellent low cost, low ESL solution, and RGCs are still popular today for some applications. 

Enter the IDC

Later, AVX further fleshed-out its low inductance MLCC offering by inventing the interdigitated capacitor (IDC) which exhibited ESL values between that of RGC MLCCs and LICAs.  IDC required an intermediately complex mounting scheme (interdigitated mounting pads and complex via schemes, etc.), and was significantly more expensive than standard configuration MLCCs.  Even though it was complex and somewhat expensive, IDCs also enjoyed great success as they presented a solution with performance nearing LICA that did not require exotic surface mounting technology (C4 and the like).  Many millions of computer microprocessors were decoupled using IDCs, and IDCs are still popular for certain applications today.

Enter the KISS Principle

The low ESL market was still not satisfied by the above solutions however, and microprocessor manufacturers and their circuit designers kept looking for low ESL solutions that are simple and cheap.  Over the above time period, and as MLCC miniaturization efforts began, it came to the realization of designers that ESL values of large case size, standard configuration MLCCs are significantly higher than the ESL values exhibited by their smaller case “brethren.”  Using this knowledge, designers started designing with standard configuration MLCCs, using the smallest case size where acceptable capacitance values were generally available “on the cheap” (see A Farad on the Head of  Pin for Free for details). 

Since EIA 0402 and EIA 0201 standard configuration MLCCs exhibit ESLs that are on the order of 0612 IDCs, and since Class 2 dielectric versions are generally available in these case sizes with capacitance values as high as 10 µF and 1 µF for 0402 and 0201 sizes respectively, many designers have pursued the strategy of using standard small case MLCCs.  A further advantage of this approach is that it allows relatively simple, standard circuit designs.  This is also advantageous as small case standard configuration MLCCs are now generally available and are priced most competitively compared to other low ESL solutions.  Because of these advantages, this approach is now the generally accepted solution for high speed decoupling and is used in many, if not most, high speed decoupling applications today.

Enter “Other” Solutions

Over this time frame, other low ESL MLCC configurations have been realized as well, such as controlled ESR IDCs, interposer MLCCs and the like.  These solutions have also suffered from cost and complexity however, and the simple, low cost solution of using numerous small case, standard configuration MLCCs, combined with prudent circuit design (as discussed in Part 1 of this series) has become the prominent solution, with other configurations, such as RGC MLCC, generally being used in specialized designs that cannot utilize very small case size components.

Closing Thoughts

Although, as stated in Part 1 of this series, ESL is more important than capacitance for decoupling at high frequencies, it is still important to understand and compensate for the fact that the capacitance of Class 2 dielectric MLCCs may drop significantly when a DC voltage is applied (even with voltages as low as those used to power modern microprocessors).  An understanding of this phenomenon is provided in Venkel’s technical paper, “Testing and Measurement Practices of High Capacitance Ceramic Capacitors,” and is defined for MLCCs of interest in Venkel’s “Electrical Characteristics Data (ECD) for Ceramic Capacitors.”  Well, that’s it for MLCCs for high speed decoupling. My next post will cover ESR…TTFN!

Tags: Capacitors, Ceramic Capacitors, Low Inductance

Decoupling Part 1: The Basics

Posted by Mike Randall on August 07, 2014

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This is Part 1 of a Two Part Series

  • Decoupling Part 1:The Basics
  • Decoupling Part 2:Low Inductance MLCCs

One of the largest uses of ceramic capacitors in the electronics industry is for decoupling.  Decoupling is commonly referred to as a methodology used to provide a localized source of electrical energy to a circuit in order to prevent unwanted changes to the supply voltage.  Decoupling is commonly used in power delivery circuits in an application that involves a relatively high switching load.  Typical examples include power supplies and microprocessors. 

What happens?

For example, when the switching demand becomes too high at a microprocessor, the supply voltage may “droop” or be reduced to a level that is unacceptably low for the “on” state of one or more switches within the microprocessor.  When this occurs, switch state errors can happen and the microprocessor may either crash or do something different than you asked it too.  In order to prevent this from happening, designers place decoupling capacitors local to the microprocessor from the power line to ground.  In this configuration, the decoupling capacitors charge to the supply voltage value during normal operation, while blocking DC power transfer to ground.  When the switching load at the microprocessor becomes high, the charged, local decoupling capacitors become local energy sources as the supply voltage begins to drop due to the high demand at the microprocessor.  These “little batteries” quickly supply charge to the supply power in order to ensure that the supply voltage is maintained during conditions of high load from the microprocessor.  In that manner, they “decouple” the microprocessor from the power supply.

So now that we know what decoupling is, what are some “rules of thumb” with regard to decoupling?  From the most basic standpoint, we want to ensure that enough charge is always available to the load and that it is available quickly enough to prevent unacceptable voltage droop (or unacceptable change in waveform) and we want to do this all in an economic manner.  But first we will cover some decoupling history in order to provide perspective.

History of Decoupling

Approaches to decoupling have changed over time.  Originally, multiple tiers of decoupling were used and the each tier decoupled into another tier closer to the load.  Typically very high value aluminum electrolytic capacitors would be used at the power supply which would serve to provide third tier decoupling to tantalum capacitors placed midway between the power supply and the microprocessor, which would provide second tier decoupling to ceramic capacitors placed near the microprocessor load, which provided first tier decoupling to the load or microprocessor.  While this methodology works well, it is relatively expensive and design engineers have spent considerable resources finding simpler schemes for decoupling.

As power supplies have evolved over time to higher switching frequencies, tier 3 and tier 2 have been reduced or combined or eliminated and an emphasis has been placed on power distribution quality of the power supply to tier 1 and the load over a broad range of frequencies.  Additionally, the evolution of microprocessors to include more on chip decoupling capacitance (tier 0) has somewhat reduced, the demands for tier 1 decoupling in general.  Additionally, microprocessor switching frequencies have largely stabilized over time due to power savings requirements as well as the advent of multicore microprocessors.  All of these factors have resulted in an evolution in decoupling that has enabled more economical, smaller, and generally better power distribution to a microprocessor (or switching load).

This leaves optimization of tier 1 decoupling.  The goal of Tier 1 decoupling is to feed enough charge to tier 0 decoupling capacitance, resident within the microprocessor quickly enough to prevent significant voltage droop or other signal degradation.  Multilayer ceramic capacitors (MLCCs), with their small size and low ESR (i.e., ability to discharge very quickly) are ideal for this application and as such are the capacitor of choice for this application. 

Some Guidelines

The amount of capacitance that you need will depend upon your situation (mostly switching speed and switching energy).  The effect of the combination of switching speed and switching energy upon voltage droop is characterized by the equation:      

where:
  • VDroop is voltage droop                  
  • I is current (Amperes)
  • ω is angular frequency (f) and is equal to 2πf
  • C is capacitance (Farads)
  • ESL is equivalent series inductance (Henries)
  • ESR is equivalent series resistance (Ohms)

Typically multiple MLCCs are placed locally in parallel in a decoupling design.  The values depend upon the situation with more capacitance being needed at lower frequencies and lower ESL being needed at higher frequencies.  In practice, several each of several different capacitance values are placed locally;  tier 3 capacitors near the power supply and the tier 1 capacitors near the switching load or microprocessor. 

As an example, the above equation may be used to estimate maximum voltage droop in the case of multiple 10µF, 1µF, and 0.1µF and 0.01µF may be placed near the microprocessor to ensure that voltage droop is less than a specified value over a range of frequencies of interest.  If 10 each of the above 10µF, 1µF, and 0.1µF MLCCs and 20 each of the 0.01µF MLCCs are used very close to a microprocessor that can pull 25A at 2V with no more than 5% voltage droop allowed, the above configuration could be used to keep voltage droop less than 5% over the range of 1 MHz to 100 MHz.  The tier 0 capacitance (on chip) would be used to keep voltage droop low at higher frequencies (up to ~ 3Ghz or more).

The Process

In practice, the designer will determine the impedance needed for his or her power distribution network design using the relation:

where: Z is impedance (Ohms)

The designer will also calculate the tier 3 capacitance needed to ensure that the voltage does not droop below the acceptable limit at lower frequencies using the relation:

where: Δtlf is the maximum allowable rise time for low frequency (sec)

The designer will also calculate the inductance that his or her design must stay below on the tier 1 side of the design using the relation:

lmax

where: Δthf is the minimum allowable rise time at highest frequency (sec)

 Other Considerations

All capacitors are placed in parallel in the circuit from power to ground.  When selecting capacitors for the lower frequency end of the spectrum (i.e., tier 3 and tier 2) the designer selects a combination of capacitors with high capacitance and low ESR in order to minimize VDroop.  When selecting capacitors for the high frequency end of the application, the designer selects a combination of capacitors having lower capacitance and minimal ESL such that the circuit stays below the maximum impedance allowed at the high end of the application frequency range. 

Since a broad array of capacitance values will be used, it is important to select a combination of C, ESL and ESR that ensures avoidance of sharp peaks in Z due to anti-resonances between the different capacitance values placed in parallel.  The designer will also take advantage of the multiple resonance frequencies that a broad of capacitance values affords in order to minimize Z over a broad spectrum.

Circuit Design Considerations

It is also important to remember that, for tier 1 decoupling, the rest of the decoupling circuit design is important as well, as inductance of the entire circuit must be minimized.  To achieve this, tier 1 MLCCs are generally placed as close as possible to or directly on the microprocessor package.  To further reduce inductance, tier 1 MLCC may be placed on the back of the microprocessor package, directly beneath the microprocessor die.  To further ensure that circuit inductance is minimized, the MLCC connection to the circuit board, as well as the power and ground interconnects, should be designed to minimize current loops (inductance) using special solder pad and via design and placement, as well as use of multiple vias per mount where prudent. 

To reduce tier 1 inductance even further, use of specially designed, low ESL MLCCs may be used.  That will be the subject covered in Part 2 of this series.  I hope that you found this valuable…TTFN!

Tags: Ceramic Capacitors, decoupling, capacitor

Deviant Behavior Part 3: Seen and Not Heard

Posted by Mike Randall on June 30, 2014

 

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When it comes to electronics, silence is golden. Electronics designers work long and hard to reduce or eliminate sources of noise from electronic components such as fans, transformers, disk drives and the like.  But have you ever thought about those innocent looking little MLCCs on your board?  If you use a lot of Class 2 dielectric MLCCs (X5R, X6S, X7R and the like), you may want to look twice, as you may have a “choir of singing MLCCs” on your board.

You Don’t Get Something for Nothing

You see, stuffing all of that capacitance into a tiny little package requires the use of dielectric materials that have a very high dielectric constant (K), which is basically a unitless measure of the charge density of active dipoles in a given volume as compared to an equivalent volume of vacuum.   All other things being constant, capacitance per unit volume increases linearly as K increases.  Because of this, most Class 2 MLCC are made with high K (i.e., K = 2500+) ceramic materials, that are almost all based on the “magical” crystal chemistry of barium titanate (BaTiO3) or BT.  But BT also has a “bad side.”

God’s Gift to Ceramics

Barium titanate is an amazing material.  It is not found in nature and was originally developed in the early 1900s for use in radar systems for its ferroelectric properties.  These properties are discussed in Venkel’s White Paper: Testing and Measurement Practices of High Capacitance Ceramic Capacitors and those properties are profound...so much so that one of my professors at Alfred University deemed it “God’s Gift to Ceramics.” 

While these ferroelectric properties enable dielectrics with extremely high K, they also result in movement of the internal crystal structure (i.e., piezoelectric effect and to a lesser extent, electrostriction) when an electric field is applied, and they also result in a build-up of charge (electric field) when an external mechanical stimulus is applied.  This movement of the internal structure can translate to the exterior of the material and can be quite significant.  Because of this, BT can be used to make buzzers, speakers and other devices requiring mechanical displacement, as well as devices that convert mechanical stimulus into electrical charge, such as igniters. That mechanical displacement can make noise, and that noise can add up if multiple MLCCs “see” a similar and significant electronic signal in the audible range resulting in a “choir of singing MLCCs.”  This effect can be further “amplified” if the MLCCs are rigidly coupled to the circuit board in a manner that results in amplification of the resulting pressure waves, causing a makeshift speaker of sorts.  This effect becomes more prominent if the board is relatively large.

It should be noted that the above piezoelectric and electrostrictive effects also “work in reverse,” meaning that mechanical displacement of Class 2 MLCCs from the exterior of the MLCC device (i.e., noise, vibration or the like) may resulted in added electrical noise to your signals.  This is called “microphonic effect” and has the same scientific bases of operation.

Trade-Off Time

So here is the conundrum.  How do you take advantage of BT’s high K for your high capacitance density MLCC needs, while minimizing piezoelectric and/or electrostrictive side effects that accompany ferroelectric behavior and that result in an annoying buzzing when a signal of significant field, in the audible frequency band is applied (or half the audible band, in the case of electrostriction, due to its frequency doubling effect)?  The answer lies in the trade-offs that you are willing to take in your design. 

You can avoid signals in the audible frequency range.  You can also reduce the amplitude of the signal such as by reducing ripple in a circuit or the like.  You can also change the waveform, for example to a relatively gentle sinusoid from a sharper digital waveform.

You can also use a device that will effectively “see” a smaller signal field.  That can be accomplished using an MLCC with a higher voltage rating than is needed (i.e., one with a thicker dielectric, and thus reduced signal field).  You can also use lower capacitance values (in parallel if necessary).  This can be especially effective at reducing noise if you use a mutual cancellation approach, such as populating the board on both sides and feeding the same signal to two MLCCs that are directly opposite to each other.  Additionally, you can swap the MLCC with one having a lower dielectric constant, as this effect (e.g., d33) tends to increase with increasing K (e.g., swap an X5R for a Y5V, or an X7R for and X5R, or a C0G (Class 1) for any of these).  This will likely come at the expense of board real estate however.  If a C0G MLCC cannot be used, you may want to consider using a tantalum capacitor in place of the “singing capacitors” if the signal is appropriate so as to avoid imposing reverse polarity to the Ta caps.

You can also reduce the stiffness of the mechanical coupling of the MLCC to the board using compliant lead devices and by not using epoxy or other rigid materials to attach the MLCC to the circuit board in areas other than the terminals (typically used for wave solder attach).  Additionally, you can orient the internal electrode plates of the MLCC orthogonal to the plane of the board, which will reduce mechanical coupling to the circuit board on the Z-axis.  Further, you can populate the MLCCs toward the periphery of the circuit board as opposed to the middle of the board, but be sure to consider design rules regarding flex cracks if you do this, and to remember that local grouping of multiple MLCCs that “see” this type of signal should be avoided as the volume of the noise increases significantly when MLCCs “seeing” that type of signal are grouped. 

Seen and Not Heard

So please remember that the Class 2 MLCC in your design can produce noise (and can add noise to your signals) in certain designs.  If your design or your application needs to be quiet, you will need to select devices appropriately as well as to design your circuit so that it “speaks no evil” and “hears no evil.”  Prudent device selection and circuit design can minimize or eliminate these effects so that your capacitors can be “seen and not heard.”  I wish you well with your designs.  Until next time, TTFN!

Tags: Capacitors, Ceramic Capacitors, Ceramics

Deviant Behavior Part 2: Dude, Where’s My Capacitance?

Posted by Mike Randall on June 24, 2014

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Greetings designers!  So, you just finished your latest circuit design and you are amazed that you were able to find MLCCs that were smaller than the ones recommended by your power supply vendor.  Your circuit footprint is now smaller and the total components cost is less.  Congratulations! Give yourself a “high five” for your accomplishment!

No High Five for You!

The next week your design “crashes” during evaluation, due to excessive voltage drop, or to out of spec. ripple, or to…  You ask yourself, “What happened?”  You used the same capacitor values with the same “dielectric” that the power supply vendor recommended (“X5R”…whatever that is).  Heck, you even used the same voltage rating that they recommended.  What could have happened?  Does size really matter that much?

Well, while you thought that the power supply specification was just old, and not up to date with the latest miniaturized capacitor offerings, it may be that the power supply vendor actually was current and was looking out for you, having tested their design recommendations (and perhaps others that didn’t work as well) prior to publication.    

Not Your Father’s Capacitor

You see, not all X5R dielectrics and MLCC designs are the same.  The X5R specification simply indicates an “envelope” that the dielectric will stay within throughout the temperature range between -55C to +85C (i.e., ≤+/-15% deviation in capacitance (typically measured at 1 VAC@1 KHz and 0VDC), relative to the “room temperature” capacitance (typically measured at either 20C or 25C)).  It also indicates that it meets some type of reliability specification (which varies from manufacturer to manufacturer and with voltage rating) at 85C temperature and at rated voltage (or a multiple of rated voltage).  Unfortunately, the specification does not cover allowable variation in capacitance with applied DC voltage, which can be quite considerable, and can vary greatly depending upon the chemical composition of the dielectric as well as the MLCC design.  The reasons for this are based primarily in the chemistry of the ferroelectric dielectric materials used in the Type 2 MLCC, as well as in the MLCC design (primarily dielectric thickness) of the capacitor.  Venkel recently published an excellent technical paper (link) that discusses the detail behind these reasons.

With progress in MLCC development (more capacitance in a smaller package), MLCC manufacturers have moved the boundaries of performance in order to meet the specifications that they have to meet (e.g., primarily X5R or other temperature characteristic, as well as specified reliability).  In some cases, that has resulted in compromise of other factors (e.g., sensitivity of capacitance to voltage in this case).  Small “tweaks” in dielectric chemistry or MLCC design, introduced with each new generation of MLCC, can have significant influence on these other factors (such as capacitance sensitivity to voltage).  Not wanting to “air their dirty laundry” some manufacturers have been reluctant to publish these data, in some cases, to the detriment of their customers.

This Could Happen to You

As a result some circuit designers have been “blindsided” when selecting MLCCs for their designs.  For example, capacitance can decrease as much as 80% or 90% when rated voltage (DC) is applied as compared to the 0VDC applied voltage in the manufacturer’s specification.  Imagine purchasing a 10µF 0402 MLCC and finding that it is really a 1µF capacitor at rated voltage, and ask yourself can your designs withstand that much change in capacitance?  If so, fine.  If not, you should choose a different capacitor. 

In order to make an informed decision, look at the voltage sensitivity curve for the device you are interested in (link for examples).  If you cannot accept the variation indicated in your design, look at the voltage sensitivity of other capacitors (higher voltage rating, larger case size, or less sensitive dielectric, or higher capacitance value, or the like) until you find a suitable solution to your design needs.  Whatever you do don’t assume that Type 2 MLCCs have stable capacitance with respect to applied voltage, because typically, they don’t.

Parting Shots

So go forth and prosper using the best and most economical capacitor solution that you can find to meet the needs of your designs.  Just be sure to “read the fine print” with regard to the performance aspects that are important to you.  If the data that you need aren’t available, be sure to ask for it (http://www.venkel.com/technical/electrical-characteristics-data).  The last thing that you want is to have your circuit fail in performance testing because of your improper selection of a sub-penny component.  Now redesign that circuit, test it and give yourself that “high five!

Tags: ECD, Ceramic Capacitors

Testing, Measurement, Accuracy, Results - High Capacitance Ceramic Capacitors

Posted by Nathan Bailey on June 16, 2014

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Set-up, measurement, accuracy, test method, result; Words that test engineers know and live by.  We all want accurate results and if you ask 10 test engineers, you might get 10 different answers on how to get there.   When you tell a test engineer that his or her results are incorrect, they may take offense and push back and say they’re ones that are correct and its your products that are out of specification. 

 This is what we find when encountering measurement or correlation issues when endeavoring to measure high value (typically considered to be > 1uF) Multi-Layer Capacitors or MLCC’s.  The inability to accurately measure high value MLCC’s has been an issue in our industry for years with the advent of high value MLCC’s, the issue does not appear to be going away anytime soon. This is due to the fact that many capacitance testers and LCR meters used throughout the industry are not designed to, nor have the capability to correctly measure capacitance of high capacitance (Hi-Cap) MLCCs. This is the case whether we are measuring capacitors at 1 VAC and 1 KHz or 0.5 VAC and 120 Hz. The inability to correctly measure high capacitance MLCCs is due to two reasons. First, many LCR meters do not have the capability of supplying enough current to the capacitor being tested at 1KHz and 1 VAC, resulting in a reduced measurement voltage which results in an artificially reduced capacitance reading. Second, Hi-Cap MLCCs typically utilize Class 2 dielectrics (e.g. X5R, X6S, X7R, X7S, etc.) that are sensitive to test voltage in the sense that changing test voltage results in change in capacitance. Since Class 2 dielectrics are typically made with ferroelectric dielectric materials that are non-linear in behavior with respect to test voltage, this change in capacitance will occur. These two reasons plus the ageing phenomenon (discussed in an upcoming Blog) exacerbates the issue and explains why it is essential to ensure that you apply the correct test voltage to the MLCC when measuring or testing a capacitor and trying to obtain its actual capacitance value. Incorporating the right bridge and applying the correct parameters is essential in obtaining an accurate capacitance measurement.

 To ensure that capacitance is correctly measured, each capacitor must be tested under the correct conditions. The correct conditions for measurement depend upon the capability of the measurement equipment as well as the nominal capacitance to be measured. Since Capacitance measurements are typically performed in the low range of the frequency scale around 120Hz-1KHz, the capacitive reactance (XC) typically dominates the impedance equation, and Z may be estimated from the relationship:

capformulaFrom this relationship, it is clear that the impedance of a capacitor is dependent upon frequency and capacitance value. So why does the electronic industry make a standard to measure a 10uF MLCC at 1KHz but a 15uF at 120Hz?

In my next post I will discuss this in more detail and demonstrate how that works in the form of a graph and some additional data.  Then,  I will continue with providing information and data to support the theory that MLCC’s with the value of 10uF should also be tested at 120Hz and not 1kHz. This should “stir the pot” a bit as I have encountered numerous instances where this is the case when older test equipment is used throughout the industry.  Some customers have re-evaluated their test frequencies based on cap value and the type of test equipment they have and have done so with good success.

 Hope to see you next month and as you know – “Engineers make the world go around! ”TM

Tags: Capacitors, Ceramic Capacitors, Ceramic

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