Equivalent series resistance or ESR is a measure used to characterize the real portion of the impedance of a capacitor.  This is the resistance (R) that the impedance curve typically hits at series resonance, and ESR is commonly used to characterize that value.  For a perfect capacitor ESR is 0.  But, with the possible exception of Cronuts^TM, nothing is perfect, so we mortals must accept real capacitors. 

At and near resonance frequency, ESR defines the impedance (Z) of a capacitor.  At lower frequencies, impedance is largely controlled by capacitive reactance (X_C) and at higher frequencies Z is controlled mainly by inductive reactance X_L.  Inductive reactance is controlled by inductance (L), and is commonly characterized by equivalent series inductance or ESL, in a manner analogous to using ESR for R.  A typical model for a real capacitor at frequencies below and near resonance is a capacitor and a resistor in series as illustrated above.

Fun with Math

ESR is related to other performance measures of a capacitor as well.  Dissipation factor or df is the measure of the ratio of a capacitor’s real resistance (ESR) to its capacitive reactance (X_C).  Df is equivalent to the tangent of the angle between ESR and X_C as illustrated above.  This angle is commonly called delta (δ) and so df = tan(δ).  The cartoon above illustrates the geometry between X_C, ESR and δ. 

The inverse of df is the quality factor of a capacitor, also known as Q.  So Q is a measure of the “perfectness” of a capacitor as Q=1/tan(δ).  Since tan(δ) = ESR/X_C, Q = X_C/ESR.  Following this logic, ESR = tan(δ)/X_C = 2πfC·tan(δ) = 2πfC·df and the power dissipated by a capacitor at a given frequency near resonance is P = I²·Z ~ I²·ESR.  So, as ESR is increased, the amount of power dissipated in the capacitor for a given current flow (I) increases.

What does all that mean?

So now that we know what ESR is and how it works, when should we select a capacitor with a higher ESR and when should we select a capacitor with a lower ESR?  That seems obvious, right?  We want to be as close to perfect with our capacitor as we can be, right?  Not so fast my friends!  Zero ESR, just like Cronuts^TM, may not always be your best choice in our real world.   

When to Use Low ESR

There are situations where it is true that, lower ESR in the capacitor selected is better.  For example in band pass or notch filtering, the high Q (and low ESR) of the device selected helps to increase the amount of signal passed over the range of frequency of interest while blocking signal outside of the frequency range of interest.  In this case, the capacitance value is selected, in combination with the knowledge of the device’s inductance, in order to achieve resonance at the frequency of interest (f₀), using the relation f₀ = 0.1592·(L·C)^-1/2 = 1/[2π√(L·C)].  Selection of the appropriate capacitor value will define a frequency “notch” wherein the impedance is suitable to pass current over a range of frequencies that is defined by its associated impedance curve.  The edges of this frequency range are typically defined by a 3 decibel (dB) change in signal intensity from the base Z curve and the effectiveness of the filter is typically defined by the rate of change in passed frequency intensity with changing frequency, in units of decibel per decade of frequency or dB/decade.  High Q and low ESR capacitors are used in these applications because the lower the ESR, the lower the impedance at resonance and the greater the amount of signal passed at f₀ and the higher the dB/decade of the filter.   As a definite and consistent frequency (f₀) is needed for the circuit to filter properly, highly consistent capacitance values are needed as are consistent ESL and ESR, so that the filter will perform the same in all devices using the design.  Because of this, it is prudent to use tight capacitance tolerance, low ESR NPO/C0G MLCCs for this application such as those available through Venkel.  For this application, G (+/-2%) tolerance class or better C0G/NPO MLCCs are typically used.

In another application (when designing for power distribution over low-to-moderate frequencies), it is important to strive for a relatively flat impedance curve over a broad range of frequencies.  Tantalum capacitors are ideal for this application and use of low ESR Ta capacitors can enable the use of lower part counts in achieving your “low and flat” Z goal.  Such low ESR Ta capacitors are also available through Venkel.  Another potential option for this application is selection of controlled ESR MLCCs, having increased ESR over standard MLCC designs.  Controlled ESR MLCCs also typically have low ESL, making them ideal for applications requiring higher switching frequencies.  Unfortunately, however, controlled ESR MLCCs are not generally available and they are typically very expensive.  Because of these factors, low ESR Ta is still the capacitor of choice for this application.  And if higher switching frequency is needed, standard configuration MLCCs or low ESL MLCCs are used in the power distribution network (PDN) to complement the low ESR Ta capacitors as needed.

When Low ESR can be a Problem

As with Cronuts^TM, it is possible however to “go too far” with low ESR, and the designer must be careful to avoid these situations.  An example of this is when the ESR of the capacitor selected is very low and the range of application frequencies used in the design includes frequencies that are significantly higher than the series resonance frequency (f₀) or SRF of the capacitor selected, such that parallel resonance occurs.  When use frequencies exceed the parallel resonance frequency (PRF) of at least one capacitor in the circuit, a low ESR may not provide enough impedance to the resonating portion of the circuit in order to properly dampen the parallel resonance.  In this case, a “tank oscillator” is established and the impedance curve may have sharp, resonance peaks, in direction opposite to the series resonance peak on the impedance curve, over the high frequency portion of the use frequency range of the impedance curve.  This may result in unwanted behavior of the circuit, such as the introduction of noise to the circuit or the like.  These phenomena are generally undesirable and may be addressed via proper capacitor selection, including proper selection of capacitance value, tolerance, and increased ESR values, such that parallel resonance is avoided, or at least dampened properly.  Parallel resonance can also be avoided or reduced by mounting the high frequency MLCC(s) selected for you design onto your circuit in a manner such that the internal electrodes are oriented vertically.  This, in effect, removes the odd harmonics of the parallel resonance of a capacitor, including the first harmonic, and increases the usable frequency range to below the second harmonic of the PRF. 

In Conclusion:

So, we have discussed ESR and associated loss factors and we know that, generally, low ESR is good.  We also know now that, for band pass and similar filtering situations, it is important to use tight tolerance, high Q, low ESR capacitors (NPO/C0G MLCCs) with consistent capacitance value, consistent ESR and consistent ESL.  We also know that low ESR Ta capacitors are generally the capacitor of choice when designing for flat Z over a broad range of frequencies from low-to-intermediate frequencies for power distribution applications or the like.  Finally we know to be careful to avoid deleterious effects of parallel resonance when selecting capacitors for high frequencies, and that we can do this through prudent capacitance value selection as well as use of moderate ESR MLCCs and/or making sure that the frequency range of our design does not encroach a PRF of any of the capacitors in the circuit.  We also know that PRF can be increased by mounting the MLCC of interest with its internal electrodes oriented vertically so as to eliminate odd harmonics (including the first PRF harmonic). 

Whew!  That was exhausting…I need a Cronut^TM!  TTFN!

This is Part 3 of a Four Part Series

• Part 1
• Part 2

Hello fellow engineers and circuit problem solvers. We have a lots going on ‘round here and as we keep adding important and relevant data to our website and catalog. Just like you, there is much more to do but we are well on our way and making improvements in many areas. This month’s blog is #3 in a series of 4 related blogs regarding the testing and best practices for testing high value or high capacitance MLCC’s. This month will blog will expand on the information we have discussed and the 4th in the series will end with a general summary of all the aforementioned best practices for testing these high value MLCC’s.

What happens when you attempt to measure a high value MLCC with an LCR tester not suited (i.e.- it does not have and adequate power supply to provide the DUT the with the necessary rms test voltage) for measuring high value MLCC’s with low Z and ESR? Answer: The tester will not supply the necessary AC test voltage and it will drop below a minimum specified level to provide the DUT with enough AC test voltage giving you an artificially low capacitance reading and leading you to believe that the capacitors are out of specification. You may set the test voltage to 1.0 V but many testers will not provide the true “selected” voltage and the actual test voltage applied to the DUT will probably be in the 0.3V-0.7V range due to the low impedance. Following is a graph of a table I supplied in the previous post on this subject showing capacitor impedance at 120Hz and 1kHz and the current required to the test voltage (Arms):

This is Part 1 of a Two Part Series

• Decoupling Part 1:The Basics
• Decoupling Part 2:Low Inductance MLCCs

One of the largest uses of ceramic capacitors in the electronics industry is for decoupling.  Decoupling is commonly referred to as a methodology used to provide a localized source of electrical energy to a circuit in order to prevent unwanted changes to the supply voltage.  Decoupling is commonly used in power delivery circuits in an application that involves a relatively high switching load.  Typical examples include power supplies and microprocessors. 

What happens?

For example, when the switching demand becomes too high at a microprocessor, the supply voltage may “droop” or be reduced to a level that is unacceptably low for the “on” state of one or more switches within the microprocessor.  When this occurs, switch state errors can happen and the microprocessor may either crash or do something different than you asked it too.  In order to prevent this from happening, designers place decoupling capacitors local to the microprocessor from the power line to ground.  In this configuration, the decoupling capacitors charge to the supply voltage value during normal operation, while blocking DC power transfer to ground.  When the switching load at the microprocessor becomes high, the charged, local decoupling capacitors become local energy sources as the supply voltage begins to drop due to the high demand at the microprocessor.  These “little batteries” quickly supply charge to the supply power in order to ensure that the supply voltage is maintained during conditions of high load from the microprocessor.  In that manner, they “decouple” the microprocessor from the power supply.

So now that we know what decoupling is, what are some “rules of thumb” with regard to decoupling?  From the most basic standpoint, we want to ensure that enough charge is always available to the load and that it is available quickly enough to prevent unacceptable voltage droop (or unacceptable change in waveform) and we want to do this all in an economic manner.  But first we will cover some decoupling history in order to provide perspective.

History of Decoupling

Approaches to decoupling have changed over time.  Originally, multiple tiers of decoupling were used and the each tier decoupled into another tier closer to the load.  Typically very high value aluminum electrolytic capacitors would be used at the power supply which would serve to provide third tier decoupling to tantalum capacitors placed midway between the power supply and the microprocessor, which would provide second tier decoupling to ceramic capacitors placed near the microprocessor load, which provided first tier decoupling to the load or microprocessor.  While this methodology works well, it is relatively expensive and design engineers have spent considerable resources finding simpler schemes for decoupling.

As power supplies have evolved over time to higher switching frequencies, tier 3 and tier 2 have been reduced or combined or eliminated and an emphasis has been placed on power distribution quality of the power supply to tier 1 and the load over a broad range of frequencies.  Additionally, the evolution of microprocessors to include more on chip decoupling capacitance (tier 0) has somewhat reduced, the demands for tier 1 decoupling in general.  Additionally, microprocessor switching frequencies have largely stabilized over time due to power savings requirements as well as the advent of multicore microprocessors.  All of these factors have resulted in an evolution in decoupling that has enabled more economical, smaller, and generally better power distribution to a microprocessor (or switching load).

This leaves optimization of tier 1 decoupling.  The goal of Tier 1 decoupling is to feed enough charge to tier 0 decoupling capacitance, resident within the microprocessor quickly enough to prevent significant voltage droop or other signal degradation.  Multilayer ceramic capacitors (MLCCs), with their small size and low ESR (i.e., ability to discharge very quickly) are ideal for this application and as such are the capacitor of choice for this application. 

Some Guidelines

The amount of capacitance that you need will depend upon your situation (mostly switching speed and switching energy).  The effect of the combination of switching speed and switching energy upon voltage droop is characterized by the equation:      

• V_Droop is voltage droop                  
• I is current (Amperes)
• ω is angular frequency (f) and is equal to 2πf
• C is capacitance (Farads)
• ESL is equivalent series inductance (Henries)
• ESR is equivalent series resistance (Ohms)

Typically multiple MLCCs are placed locally in parallel in a decoupling design.  The values depend upon the situation with more capacitance being needed at lower frequencies and lower ESL being needed at higher frequencies.  In practice, several each of several different capacitance values are placed locally;  tier 3 capacitors near the power supply and the tier 1 capacitors near the switching load or microprocessor. 

As an example, the above equation may be used to estimate maximum voltage droop in the case of multiple 10µF, 1µF, and 0.1µF and 0.01µF may be placed near the microprocessor to ensure that voltage droop is less than a specified value over a range of frequencies of interest.  If 10 each of the above 10µF, 1µF, and 0.1µF MLCCs and 20 each of the 0.01µF MLCCs are used very close to a microprocessor that can pull 25A at 2V with no more than 5% voltage droop allowed, the above configuration could be used to keep voltage droop less than 5% over the range of 1 MHz to 100 MHz.  The tier 0 capacitance (on chip) would be used to keep voltage droop low at higher frequencies (up to ~ 3Ghz or more).

The Process

In practice, the designer will determine the impedance needed for his or her power distribution network design using the relation:

where: Z is impedance (Ohms)

The designer will also calculate the tier 3 capacitance needed to ensure that the voltage does not droop below the acceptable limit at lower frequencies using the relation:

where: Δt_lf is the maximum allowable rise time for low frequency (sec)

The designer will also calculate the inductance that his or her design must stay below on the tier 1 side of the design using the relation:

where: Δt_hf is the minimum allowable rise time at highest frequency (sec)

 Other Considerations

All capacitors are placed in parallel in the circuit from power to ground.  When selecting capacitors for the lower frequency end of the spectrum (i.e., tier 3 and tier 2) the designer selects a combination of capacitors with high capacitance and low ESR in order to minimize V_Droop.  When selecting capacitors for the high frequency end of the application, the designer selects a combination of capacitors having lower capacitance and minimal ESL such that the circuit stays below the maximum impedance allowed at the high end of the application frequency range. 

Since a broad array of capacitance values will be used, it is important to select a combination of C, ESL and ESR that ensures avoidance of sharp peaks in Z due to anti-resonances between the different capacitance values placed in parallel.  The designer will also take advantage of the multiple resonance frequencies that a broad of capacitance values affords in order to minimize Z over a broad spectrum.

Circuit Design Considerations

It is also important to remember that, for tier 1 decoupling, the rest of the decoupling circuit design is important as well, as inductance of the entire circuit must be minimized.  To achieve this, tier 1 MLCCs are generally placed as close as possible to or directly on the microprocessor package.  To further reduce inductance, tier 1 MLCC may be placed on the back of the microprocessor package, directly beneath the microprocessor die.  To further ensure that circuit inductance is minimized, the MLCC connection to the circuit board, as well as the power and ground interconnects, should be designed to minimize current loops (inductance) using special solder pad and via design and placement, as well as use of multiple vias per mount where prudent. 

To reduce tier 1 inductance even further, use of specially designed, low ESL MLCCs may be used.  That will be the subject covered in Part 2 of this series.  I hope that you found this valuable…TTFN!

Ceramic versus Film Capacitors

As we have discussed, MLCCs (both Class 1 and Class 2) have advanced greatly with time.  I believe that the rate of advancement of Class 1 MLCC has been faster than that of film capacitors.  I believe that this disparity in advancement has progressed to the point that there is now a pretty clear winner for small case surface mount devices (EIA 1812 and below)…and that winner is…envelope please…COG MLCC.  “Based on what,” you ask?  Let’s explore some more.

What’s Important?

Let’s start with our “Farad on the Head of a Pin for Free” set of goals.  The two types of film capacitor dielectrics that we will use in the comparison are PPS (polyphenylene sulfide) and PEN (polyethylene naphthalate) as these are the most generally available film dielectrics in a surface mount small case configuration. The smallest generally available case size for C0G MLCC is EIA 01005 while the smallest generally available size for film caps is EIA 0603, so C0G MLCCs are available that are ~1/64^th the volume of the smallest generally available surface mount film capacitor.  These smaller capacitors take up only ~1/16^th of the board space of the larger film capacitors (solder pads not included).  From this standpoint, C0G clearly wins. 

Also, C0G MLCC wins when comparing the highest capacitance generally available at a given rated voltage within a given case size.  For example for EIA 0805 the maximum capacitance generally available in a C0G MLCC is 0.047µF at 25Vrated, and for film capacitors (PPS) it is 0.027µF and 10Vrated.  (Note that you can get metallized acrylic film capacitors in EIA 0805 case size with a maximum capacitance of 0.15µF at 25Vrated, but that type of film dielectric is much more temperature sensitive, and exhibits a much higher dissipation factor and dielectric absorption, as well as a more limited temperature range.  So these types of film dielectrics are more suitable in comparison of tantalum capacitors or Class 2 MLCC and are not a part of this analysis).  The above results are similar for other case sizes EIA 1812 and less as well.

Now for the cost part, comparable PPS film capacitors are typically more than 2X the price of C0G MLCC, and PEN film capacitors are generally more expensive than PPS film caps.  Again C0G MLCC clearly wins. 

Hot Stuff

Let’s compare thermal stability and robustness.  The use temperature range for C0G MLCC is generally -55C to +125C.  PPS has a similar range and PEN is generally -55C to +85C, but some PEN film caps are available having use temperature range as wide as -55C to +125C as well.  Additionally, C0G MLCCs are available for high temperature applications (up to 260C+), so the edge goes to C0G MLCC again. 

Regarding temperature stability of capacitance, C0G MLCC can vary in capacitance no more than +/-30 ppm/C from -55 to +125C as compared to the room temperature (RT) value.  Assuming that RT is 20C, would allow a change in capacitance of as much as ~0.3%.  While PEN cannot meet this criterion, PPS is close so we will call it a tie.  With regard to dissipation factor (df), PEN and PPS both increase with temperature to the point that df at 125C is ~0.4 to 0.5%.  C0G MLCC generally do not exhibit df in excess of 0.1%, but df is not specified at other than RT for G0G, so we will call this a tie as well. 

With regard to thermal robustness, C0G MLCCs generally do not require special reflow profiles for surface mounting as film capacitors do, so C0G MLCC wins here.  With regard to reliability at elevated temperature, C0G MLCCs are generally highly reliable as are film capacitors.  However, C0G MLCCs are generally available with higher voltage ratings at a given capacitance within a given case size.  Also, certain film capacitors can be susceptible to humidity at elevated temperature, so the edge goes to C0G MLCC here as well. 

Other Stuff

So what’s left?  Well, with regard to dielectric absorption or the percentage of capacitance that a capacitor recharges after charging to a certain voltage, and then quickly discharging, C0G MLCC at ~0.5% is slightly better than PEN film at ~0.8%, while PPS film, at ~0.02 to ~0.05%, is the clear winner.  However, unless you are designing a circuit that is highly susceptible to the effects of dielectric absorption, such as a sample and hold analog to digital convertor circuit, this really doesn’t matter much since, even though the PPS value for dielectric absorption is ultra-low, the C0G MLCC value is also quite low (comparing favorably to other films), so the benefit is not obviously applicable in all but a few circuits.  For example in a circuit that charges to 2.5V, then quickly discharges, a C0G MLCC would re-apply a voltage of not more than ~12.5mV to the circuit, while PPS film would not re-apply more than ~1.25mV…both very low values.

With regard to electrical noise generated from mechanical shock, C0G MLCCs have been shown to be superior to film capacitors as well [i].  With regard to resistance to board flexure, film capacitors are generally thought to be more robust, but this can be situation specific as board flexure can pull off external terminations in addition to, or in lieu of, flexure cracks.  This failure mode may be more prominent in film caps as the terminals may not adhere as well, depending upon the termination configuration, materials and application process.  Flex robust C0G MLCCs are also now available, so this is nearly “a wash” with a slight edge going to film caps. 

With regard to self-healing properties, film capacitors clearly win as MLCCs do not self-heal.  However, PPS and PEN have limited to very limited self-healing capabilities compared to other film dielectrics, so this “win” is not very significant.  With regard to solvent resistance, C0G MLCCs are generally superior to film caps as well. 

In Summary

So it is pretty evident that, for small case (EIA 1812 or less) surface mount applications, with few exceptions C0G MLCC are superior to film capacitors.  Additionally, C0G MLCC are considerably more cost effective.  A very good one page summary of the advantages and disadvantages of using NP0/C0G MLCCs versus Film Capacitors .  For the applications discussed above, I think that it is pretty clear that C0G MLCCs are preferable to surface mount film capacitors, so “Winner Winner, Chicken Dinner...COG MLCC.”  TTFN!  

________________________  

Hey circuit designers!  Have you ever wondered why a circuit that you designed just didn’t act like you thought it should?  Well, that could be due to many reasons; several of which may be related to the capacitors that you selected for your circuit.  In this case you could be a victim of “deviant behavior”…behavior that differs from a norm or from accepted standards.  In this case, the standards of interest would be those set by the mythical “perfect capacitor”…the Unicorn of passive electronics. 

An Imperfect World

You see, like all electronic components, capacitors are not perfect.  The type of capacitor that you select will determine how far from perfection, or deviant the capacitor’s performance will be in your application.  Each real capacitor is a device that has not only a characteristic capacitance (C), but a characteristic resistance (R, typically termed equivalent series resistance or ESR) and an inductance (L, typically termed equivalent series inductance or ESL).  These “parasitics” can adversely affect circuit performance, but in certain situations may be used to your advantage. 

I remember how one of my sarcastic coworkers used to joke about “parasitics.”  He would say, “Shoot!  I don’t understand why our customers are so unhappy about parasitics; we ship them a free inductor and a free resistor with every capacitor!” J

Curves Ahead

Simply put, parasitics affect impedance (Z) as frequency is changed (i.e., the “Z curve”), which may affect circuit performance.  A perfect capacitor exhibits Z = 1/(2πfC) where f is frequency.  As C is increased, Z is reduced in a manner that is linear on a log-log scale (see left side of graphic above).  As f increases, Z of a perfect capacitor continues to decrease in this manner out to infinite frequency.  With a real capacitor, however, C “runs into” either R (typically ESR) or L (ESL) as f is increased, establishing either a “flat” or a minimum in the impedance curve.  If ESR is relatively low, L will largely determine this minimum and the Z curve will be V or gull wing shaped in the case of extremely low ESR.  If ESR is relatively high, R will establish a “floor” or “flat” in the Z curve over a relatively broad range of f.  At higher frequencies L dominates, as Z is ~2πfL, resulting in increasing Z as f is increased in a manner that is linear on a log-log scale (see right side of graphic above).   

You Got to Know When to Hold’em…and Know When to Fold’em

Prudent selection of capacitor type may be useful in achieving a desirable Z curve for your application.  For example, use of capacitors having moderate or high ESR, combined with low ESL, typically results in a relatively flat Z curve.  This may be useful for power delivery designs such as power delivery networks (PDNs), as a relatively “flat” impedance curve is often desirable.  Capacitors, such as controlled ESR reverse geometry or controlled ESR interdigitated capacitors (IDCs) or face down solid electrolyte tantalum (Ta) or low ESL solid electrolyte aluminum (Al) capacitors may be useful in these applications.  On the other hand, use of capacitors having very low ESR combined with low L, may be useful for inline high pass filter designs or for designs requiring high speed decoupling.  Discoidal ceramic capacitors are typically used for high pass filtering, and standard IDC or reverse geometry capacitors may be useful in filtering or high speed decoupling applications.   More recently the design community has favored use of numerous, small case size MLCC in parallel for high speed decoupling designs, as these MLCCs have moderate-to-low ESL (L), take up little space and can be used local to the decoupled device, and are relatively inexpensive.  Additionally, use of capacitors having very low ESR, combined with moderate-to-high L, may be useful in band pass filter designs. Standard MLCCs typically “fit the bill” here, and low loss (high Q), tight tolerance, type 1 dielectric capacitors such as C0G MLCC are typically used here for consistency in resonance frequency (the frequency at which C and L cross if R is 0 or is nearly 0).

A Little Help from Your Friends

Capacitor manufacturers spend significant development resources optimizing the above qualities for different applications.  With regard to parasitics, it’s all about the design, the dielectrics and the electrodes.  For example, in order to minimize ESR, MLCC developers will take advantage of high active layer counts and relatively thick electrodes.  To maximize ESR in an MLCC, special electrode designs may be used in IDC MLCC or resistors may be put in series with other MLCC using specialized termination materials or the like.   For low ESR, special low resistivity internal electrode materials, such as copper or specialized electrode designs may be used. 

Get Real

All combined, these materials and design factors may be used alone, or in combination, to optimize the C, R and L properties of a given capacitor design for one or more specific application(s) requiring a characteristic impedance (Z) curve, making it important for circuit designers to model their circuits with the real (C, R, L and Z) properties of the capacitors selected for their designs.  That way, you may be able to take advantage of that free resistor and inductor that is included with each capacitor! J (At the very least you will be able to compensate for their idiosyncraZies in your design).  Next time we will discuss part 2 of Deviant Behavior, but as Winnie the Pooh would say, “Ta ta for now!” (TTFN :-))